This data sheet provides detailed information about the Altera MAX 7000A series of programmable logic devices, including models, pins, functions, and packages.
The MAX 7000A family consists of high-density, high-performance programmable logic devices (PLDs) built on Altera's second-generation MAX architecture. These devices are fabricated with advanced CMOS technology and operate with a 3.3-V supply voltage, providing between 600 and 10,000 usable gates. They feature in-system programmability (ISP) via the IEEE Std. 1149.1 JTAG interface and support extended temperature ranges.
| Supply Voltage | 3.3 V |
|---|---|
| Usable Gates Range | 600 to 10,000 |
| Macrocells Range | 32 to 512 |
| Programming Cycles | 100 times |
| Maximum Counter Frequency | 227.3 MHz |
| Pin-to-Pin Delay | 4.5 ns |
| Compatible Logic Levels | 2.5-V, 3.3-V, and 5.0-V |
The devices operate with a 3.3-V supply voltage.
Yes, they can be programmed and erased up to 100 times.
The devices support counter speeds of up to 227.3 MHz.