MAX 7000A is a high-performance 3.3-V EEPROM-based programmable logic devices (PLDs) from Altera Corporation, built on second-generation Multiple Array MatriX (MAX®) architecture, with 3.3-V in-system programmability (ISP) and advanced pin-locking capability through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface, and it also supports IEEE Std. 1149.1 compliant built-in boundary-scan test (BST) circuitry and JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71
The document describes the MAX 7000A family of high-density, high-performance programmable logic devices (PLDs) based on Altera's second-generation MAX architecture. These devices operate with a 3.3-V supply voltage and provide between 600 and 10,000 usable gates. Key features include 3.3-V in-system programmability (ISP) via the IEEE Std. 1149.1 JTAG interface, built-in boundary-scan test circuitry, and support for JEDEC JESD-71 standard test and programming languages.
| Supply Voltage | 3.3 V |
|---|---|
| Usable Gates Range | 600 to 10,000 |
| Pin-to-Pin Logic Delays | 4.5 ns |
| Counter Frequencies | up to 227.3 MHz |
| Architecture | Multiple Array Matrix (MAX) |
MAX 7000A devices operate with a 3.3-V supply voltage.
Yes, they support 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface.
The devices support counter frequencies of up to 227.3 MHz.