The MAX 7000 is a high-performance, EEPROM-based PLD from Altera Corporation. It is based on the second-generation MAX architecture and includes both 5.0V MAX 7000 and 5.0V ISP-based MAX 7000S devices. The MAX 7000 family has a logic density range of 600 to 5,000 usable gates and a 5ns pin-to-pin logic delay.
This document is a data sheet for the Altera MAX 7000 Programmable Logic Device (PLD) family. The devices are based on second-generation MAX architecture and feature high-performance EEPROM-based programmable logic. They offer in-system programmability (ISP) via JTAG and include logic densities ranging from 600 to 5,000 usable gates.
| Usable gates | 600 to 5,000 |
|---|---|
| Pin-to-pin logic delays | 5 ns |
| Counter frequencies | up to 175.4 MHz |
| Technology | CMOS EEPROM |
| Operating voltage | 3.3-V or 5.0-V |
The logic densities range from 600 to 5,000 usable gates.
Yes, they can be programmed and erased up to 100 times.