MAX 7000AE is a high-performance 3.3V EEPROM-based programmable logic device (PLD) built on second-generation Multiple Array MatriX (MAX) architecture. It supports 3.3V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability. The device also features built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1 and supports JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71. It is pin-compatible with the popular 5.0V MAX 7000S devices and offers high-density PLDs ranging from 600 to 10,000 usable gates.
The document describes the MAX 7000A family of high-density programmable logic devices (PLDs) built on Altera's second-generation MAX architecture. These devices operate with a 3.3-V supply voltage and offer in-system programmability (ISP) via the IEEE Std. 1149.1 JTAG interface. The family includes models ranging from 600 to 10,000 usable gates, featuring pin compatibility with 5.0-V MAX 7000S devices and support for various packages including TQFP, PQFP, BGA, and PLCC.
| Supply Voltage | 3.3-V |
|---|---|
| Usable Gates Range | 600 to 10,000 |
| Macrocells Range | 32 to 512 |
| Maximum Counter Frequency | 227.3 MHz |
| Pin-to-Pin Logic Delay | 4.5 ns |
| Reprogramming Cycles | 100 times |
| Operating Temperature | Extended temperature range |
MAX 7000A devices operate with a 3.3-V supply voltage.
Yes, they are pin-compatible with the popular 5.0-V MAX 7000S devices.
The devices support in-system programmability through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface.