Update: 28 September, 2023
MAX 7000AE is a high-performance 3.3V EEPROM-based programmable logic device (PLD) built on second-generation Multiple Array MatriX (MAX) architecture. It supports 3.3V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability. The device also features built-in boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1 and supports JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71. It is pin-compatible with the popular 5.0V MAX 7000S devices and offers high-density PLDs ranging from 600 to 10,000 usable gates.
File format: PDF
Size: -
MD5 Checksum: 08C7E66669864AD1C28FACF10641370D
Publication date: 06 August, 2012
Downloads: -
PDF Link: ALTERA MAX 7000A handbook(1) PDF