MAX 7000A is a high-performance 3.3V EEPROM-based programmable logic device (PLD) produced by Altera Corporation. Its architecture is the second-generation Multiple Array MatriX (MAX). It supports 3.3V in-system programmability (ISP) and IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability. Moreover, MAX 7000AE device in-system programmability (ISP) circuitry compliant with IEEE Std. 1532, while EPM7128A and EPM7256A device ISP circuitry compatible with IEEE Std. 1532. MAX 7000A also supports JEDEC Jam Standard Test and Programming Language (STAPL) JESD-71.
This document is a data sheet for the Altera MAX 7000A family of high-density, high-performance programmable logic devices (PLDs). These devices are based on the second-generation Multiple Array Matrix architecture and utilize CMOS EEPROM technology to implement logic functions. They operate with a 3.3-V supply voltage and offer in-system programmability (ISP) via an IEEE Std. 1149.1 JTAG interface.
| Supply Voltage | 3.3-V |
|---|---|
| Usable Gates Range | 600 to 10,000 |
| Pin-to-Pin Logic Delay | 4.5 ns |
| Counter Frequency | 227.3 MHz |
The devices support counter frequencies of up to 227.3 MHz.
The devices can be programmed and erased up to 100 times.
The devices operate with a 3.3-V supply voltage.