The document details the EPM5016 through EPM5192 family of CMOS EPLDs based on the MAX 5000 architecture. These devices combine the speed and ease of use of PAL devices with the density of programmable gate arrays, offering combinatorial delays as low as 15 ns and counter frequencies up to 100 MHz.
The architecture features Logic Array Blocks (LABs) containing macrocell arrays, expander product-term arrays, and decoupled I/O blocks. Higher-density devices utilize a Programmable Interconnect Array (PIA) for routing between multiple LABs. The family is supported by MAX+PLUS and MAX+PLUS II development tools.
| Combinatorial delays | 15 ns |
|---|---|
| Counter frequencies | up to 100 MHz |
| Pipelined data rates | 100 MHz |
| System clock rates | up to 66 MHz |
| Macrocell range | 16 to 192 |
Higher-speed devices achieve system clock frequencies of 66 MHz.
Logic designs are created and programmed using the MAX+PLUS and MAX+PLUS II development systems.