MAX 3000A is a high-performance, low-cost PLD based on CMOS EEPROM developed by Altera Corporation. It uses MAX architecture and has 3.3V in-system programmability (ISP), high-density PLD, 4.5-ns pin-to-pin logic delays, MultiVoltTM I/O interface and other features.
The document describes the MAX 3000A Programmable Logic Device Family, which consists of high-performance, low-cost CMOS EEPROM-based PLDs built on a MAX architecture. These devices offer in-system programmability (ISP) via JTAG and boundary-scan test circuitry compliant with IEEE standards.
| Usable gates range | 600 to 10,000 |
|---|---|
| Pin counts | 44 to 256 |
| Logic delays | 4.5 ns |
| Counter frequencies | up to 227.3 MHz |
| Supply voltage | 3.3 V |
| Programming cycles | 100 times |
The available speed grades are -4, -5, -6, -7, and -10.
Altera's development systems for Windows-based PCs, Sun SPARCstations, and HP 9000 Series workstations support these devices.
Yes, the output drivers can be set for 2.5 V or 3.3 V, and all input pins are tolerant of 2.5-V, 3.3-V, and 5.0-V logic levels.