Altera MAX 3000A Programmable Logic Device Family Data Sheet

MAX 3000A is a high-performance, low-cost CMOS EEPROM-based PLD device family from Altera Corporation. It is based on the Multiple Array MatriX (MAX®) architecture and supports 3.3V in-system programmability (ISP). The series provides devices with 600 to 5,000 usable gates.


Altera MAX 3000A Programmable Logic Device Family Data Sheet - cover page
Brand
Altera
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
53
File format
PDF
File size
839 KB
Published
06 August, 2012
Updated
30 September, 2023
MD5 checksum
6375FD72203BAB512A8F484D429B52E5

About this manual

The document describes the MAX 3000A Programmable Logic Device (PLD) family, which consists of high-performance, low-cost CMOS EEPROM-based devices built on the Multiple Array Matrix (MAX) architecture. These devices offer high-density logic ranging from 600 to 5,000 usable gates and support 3.3-V in-system programmability (ISP) via the IEEE Std. 1149.1 JTAG interface.

What's inside

  • Device Features
  • Speed Grades
  • Package Options
  • Functional Description
  • Architecture Elements
  • Logic Array Blocks
  • Macrocells
  • Expander Product Terms
  • Development Support
  • Programming Support

Specifications

Usable gates600 to 5,000
Supply voltage3.3 V
Pin-to-pin logic delays4.5 ns
Counter frequenciesup to 227.3 MHz
I/O voltage compatibility5.0-V, 3.3-V, and 2.5-V
Reprogramming cyclesup to 100 times

Frequently asked questions

What is the maximum number of usable gates available in this device family?

The MAX 3000A devices offer high-density PLDs ranging from 600 to 5,000 usable gates.

What is the maximum counter frequency supported by these devices?

The devices support counter frequencies of up to 227.3 MHz.

How many times can the device be programmed and erased?

The devices can be programmed and erased up to 100 times.

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