The document describes the MAX 7000 family of high-density, high-performance Programmable Logic Devices (PLDs) based on Altera's second-generation MAX architecture. Fabricated with advanced CMOS technology, these EEPROM-based devices provide logic densities ranging from 600 to 5,000 usable gates and support in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface.
| Usable gates range | 600 to 5,000 |
|---|---|
| Pin-to-pin logic delays | 5 ns |
| Counter frequencies | up to 175.4 MHz |
| Operating voltage | 3.3-V or 5.0-V |
| Reprogramming cycles | up to 100 times |
The devices support counter frequencies of up to 175.4-MHz.
The devices can be programmed and erased up to 100 times.