This data sheet provides detailed information about the Altera MAX3000A programmable logic devices (PLDs), including features, characteristics, pin counts, packages, voltages, etc.
The document describes the MAX 3000A Programmable Logic Device (PLD) Family, which consists of high-performance, low-cost CMOS EEPROM-based devices built on a MAX architecture. These devices offer in-system programmability via JTAG and support counter frequencies up to 227.3 MHz with pin-to-pin logic delays as fast as 4.5 ns.
| Usable gates range | 600 to 10,000 |
|---|---|
| Logic delays | 4.5 ns |
| Counter frequencies | 227.3 MHz |
| Supply voltage | 3.3 V |
| Reprogrammable cycles | 100 times |
The MAX 3000A family provides high-density PLDs ranging from 600 to 10,000 usable gates.
The devices offer 4.5-ns pin-to-pin logic delays with counter frequencies of up to 227.3 MHz.
The devices can be programmed and erased up to 100 times.