Analog Devices ADN2805 Data Sheet Rev B

The ADN2805 is a clock and data recovery IC that provides receiver functions for 1.25 Gbps. It features locking to 1.25 Gbps NRZ serial data input, no reference clock required, loss-of-lock indicator, I2C interface, single-supply operation, low power, etc.


Analog Devices ADN2805 Data Sheet Rev B - cover page
Brand
Analog Devices
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
16
File format
PDF
File size
286 KB
Published
03 May, 2012
Updated
29 September, 2023
Model
ADN2805
MD5 checksum
7E30EBF220851258FF778DFA634A9B58

About this manual

The ADN2805 is a 1.25 Gbps clock and data recovery integrated circuit that provides receiver functions such as quantization, clock recovery, and loss‑of‑lock indication without requiring an external reference clock. It is targeted for GbE line‑card applications and operates over a temperature range of –40 °C to +85 °C.

The document includes features, applications, detailed electrical specifications, pin configuration, I²C register interface, SQUELCH mode operation, PCB design guidelines, and thermal and absolute‑maximum ratings. Key sections such as the functional block diagram, jitter specifications, and output timing are presented with tables and figures.

What's inside

  • Features
  • Applications
  • Specifications
  • Pin Configuration and Function Descriptions
  • I2C Interface Timing and Internal Register Description
  • SQUELCH Mode
  • Thermal Characteristics
  • PCB Design Guidelines

Specifications

Data Rate1250 Mbps
Power Supply Voltage3.0 – 3.6 V
Power Supply Current118 – 131 mA
Operating Temperature Range-40 °C to +85 °C
LVDS Output Swing (VOD)240 – 400 mV
Output Impedance100 Ω
I2C Clock Frequency400 kHz
Package Size5 mm × 5 mm

Frequently asked questions

What is the maximum data rate supported by the ADN2805?

The ADN2805 supports a data rate of up to 1.25 Gbps (1250 Mbps).

Does the ADN2805 require an external reference clock?

No, the device locks to the incoming data stream without an external reference clock.

How is the loss‑of‑lock indicator accessed?

The loss‑of‑lock indicator is provided on the LOL pin, which is LVTTL active‑high.

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