The document introduces AD9513 Rev. 0, an 800 MHz clock distribution integrated circuit with dividers, delay adjust, and three outputs. It is suitable for low jitter, low phase noise clock distribution and can be used in applications such as high-speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs, high-performance wireless transceivers, high-performance instrumentation, and broadband infrastructure.
The AD9513 provides three independent clock outputs that can be configured as LVDS (up to 800 MHz) or CMOS (up to 250 MHz). Each output includes a programmable divider (1‑to‑32) and a coarse phase‑select delay, with a selectable fine‑adjustable delay up to 11.6 ns. The device operates from a single 3.3 V supply and is packaged in a 32‑lead LFCSP.
Typical applications include high‑speed ADC/DAC clocking, wireless transceivers, instrumentation, and broadband test equipment. The datasheet details functional block diagrams, pin configurations, timing characteristics, phase‑noise and jitter performance, power‑management options, and layout recommendations for optimal low‑jitter operation.
| Clock Input Frequency Range | 0 – 1.6 GHz |
|---|---|
| LVDS Clock Output Frequency | 0 – 800 MHz |
| CMOS Clock Output Frequency | 0 – 250 MHz |
| Additive Output Jitter | 300 fs rms |
| Supply Voltage | 3.3 V ± 5% |
| Operating Temperature Range | -40 °C to +85 °C |
| Package | 32‑lead LFCSP |
The LVDS outputs can operate up to 800 MHz.
It requires a 3.3 V ± 5% supply.
The device has three programmable dividers, each selectable from 1 to 32.
The additive output jitter is specified as 300 fs rms.