The CDCF2509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCF2509 operates at 3.3 V VCC. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled or disabled separately via the control.
The CDCF2509 is a high-performance phase-lock loop (PLL) clock driver specifically designed to meet PC 133 SDRAM Registered DIMM specifications. It distributes one clock input to nine outputs, consisting of one bank of five and one bank of four. The device operates at 3.3V and includes on-chip series-damping resistors and a loop filter, eliminating the need for external RC networks.
| Operating Temperature Range | 0°C to 85°C |
|---|---|
| Clock Frequency Range | 25 MHz to 140 MHz |
| Jitter (Cycle-to-Cycle) @ 66-100 MHz | +/- 70 ps |
No, it does not require external RC networks because the loop filter is included on-chip.
The PLL can be bypassed by strapping AVcc to ground, which buffers CLK directly to the outputs.
A stabilization time of 1/2 ms is required after power up or signal changes.