the cdc516 is a phase-lock loop clock driver from texas instruments that is specifically designed for use with synchronous drams. it uses a phase-lock loop (pll) to precisely align, in both frequency and phase, the feedback output (fbout) to the clock (clk) input signal. the device operates at 3.3v vcc and is designed to drive up to five clock loads per output. four banks of four outputs provide 16 low-skew, low-jitter copies of the input clock. output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at the input clock. each bank of outputs can be enabled or disabled separately via the 1g, 2g, 3g, and 4g control inputs. when the g inputs are high, the outputs switch in phase and frequency with clk; when the g inputs are low, the outputs are disabled to the logic-low state. unlike many products containing plls, the cdc516 does not require external rc networks. the loop filter for the pll is included on-chip, minimizing the number of external components required and improving product reliability.
The CDC516 is a 3.3-V phase-lock loop (PLL) clock driver specifically designed for use with synchronous DRAMs. It uses an integrated PLL to precisely align the feedback output to the clock input signal in both frequency and phase. The device distributes one clock input to four banks of four outputs, providing 16 low-skew, low-jitter copies of the input clock.
| Supply Voltage (Voc) | 3 V to 3.6 V |
|---|---|
| Operating Temperature Range | 0°C to 70°C |
| Clock Frequency (fclk) | 25 MHz to 125 MHz |
| Number of Output Banks | Four banks of four outputs |
| Package Type | Plastic 48-Pin Thin Shrink Small-Outline Package (TSSOP) |
No, unlike many products containing PLLs, the CDC516 does not require external RC networks because the loop filter is included on-chip.
The device requires a stabilization time of 7 ms to achieve phase lock following power up or signal changes.
Yes, the PLL may be bypassed by strapping AVcc to ground, which buffers CLK directly to the device outputs.