TEXAS INSTRUMENTS CDC9842 PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER WITH 3-STATE OUTPUTS handbook

The CDC9842 is a high-performance clock synthesizer/driver that generates the system clocks necessary to support Pentium/82430X/82430VX and PentiumPro 82440FX chipsets. It provides four host-clock outputs (HCLKn) that are programmable to one of three frequencies (50 MHz, 60 MHz, or 66 MHz) via the SEL0 and SEL1 control inputs. Six PCI-clock outputs (PCLKn) are half the frequency of CPU clock outputs and are delayed 1 ns to 4 ns from the rising edge of the CPU clock. In addition, a universal serial bus (USB) clock output at 48 MHz (SBCLK) and three 14.318-MHz reference clock outputs (REF0, REF1, REF2) are provided. All output frequencies are generated from a 14.318-MHZ crystal input. A reference clock can be provided at the X1 input instead of the crystal input.


TEXAS INSTRUMENTS CDC9842 PC MOTHERBOARD CLOCK SYNTHESIZER/DRIVER WITH 3-STATE OUTPUTS handbook - cover page
Brand
Texas Instruments
Category
Motherboard
Document type
Datasheet
Language
English
Pages
7
File format
PDF
File size
89 KB
Published
01 August, 2012
Updated
30 September, 2023
MD5 checksum
8C869C0A6BC0077410253817671B603D

About this manual

The CDC9842 is a high-performance clock synthesizer/driver designed to generate system clocks necessary to support Pentium™/82430X/82430VX and Pentium Pro 82440FX chipsets. It provides four programmable host-clock outputs, six PCI-clock outputs, one 48-MHz USB clock output, and three 14.318-MHz reference clock outputs.

What's inside

  • description
  • functional block diagram
  • absolute maximum ratings
  • recommended operating conditions
  • electrical characteristics
  • timing requirements
  • switching characteristics

Specifications

Host-clock output frequencies50 MHz, 60 MHz, or 66 MHz
USB clock output frequency48 MHz
Reference clock output frequency14.318-MHz

Frequently asked questions

What chipsets does the CDC9842 support?

It supports Pentium™/82430X/82430VX and Pentium Pro 82440FX chipsets.

How are host-clock frequencies programmed?

They are programmable via the SELO and SEL1 control inputs.

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