Philips manuals, page 39
PHILIPS 74F38 Quad 2-input NAND buffer (open collector) handbook
74F38 is a quad 2-input NAND buffer (open collector) manufactured by Philips Semiconductors. It has an industrial temperature range available (–40°C to +85°C), a typical propagation delay of 7.0ns and a typical supply current (total) of 13mA.
PHILIPS 74F32 Quad 2-input OR gate handbook
The document is a product specification for the Philips Semiconductors 74F32 Quad 2-input OR gate, describing the features and characteristics of the product.
PHILIPS 74F3037 Quad 2-input NAND 30 driver handbook
This document describes the features and characteristics of the 74F3037 Quad 2-input NAND 30Ω driver integrated circuit produced by Philips Semiconductors, including 30Ω line driver, high speed, facilitates incident wave switching, and industrial temperature range available.
PHILIPS 74F27 Triple 3-input NOR gate handbook
The document describes the product specifications of the 74F27 Triple 3-input NOR gate, including features such as industrial temperature range, typical propagation delay, and typical supply current.
PHILIPS 74F280B 9-bit odd/even parity generator/checker handbook
This document describes the product specification of the 74F280B 9-bit odd/even parity generator/checker. The IC features high-impedance NPN base inputs for reduced loading, buffered inputs, and easy word length expansion by cascading. It is commonly used for error detection in high-speed data transmission or retrieval systems. The IC provides both even and odd parity outputs for generating or checking parity on up to 9 bits. Expansion to larger word sizes can be achieved by connecting the even parity outputs of multiple parallel devices to the data inputs of the final stage. The IC operates at industrial temperature range and has a fast propagation delay and low supply current.
PHILIPS 74F257A Quad 2-line to 1-line selector/multiplexer handbook
74F257A is a quad 2-line to 1-line selector/multiplexer with non-inverting data path and 3-State outputs from Philips Semiconductors. It can be used in the industrial range of -40°C to +85°C.
PHILIPS 74F244/74F244B Octal buffers handbook
The 74F244/74F244B is an octal buffer produced by Philips Semiconductors. It is ideal for driving bus lines of buffer memory address registers. The outputs are all capable of sinking 64mA and sourcing up to 15mA, producing very good capacitive drive characteristics. The device features two output enables, OEa and OEb, each controlling four of the 3-State outputs. The 74F244B is functionally equivalent to the 74F244. It has been designed to reduce effects of ground noise. Other advantages are noted in the features.
PHILIPS 74F166 8-bit bidirectional universal shift register handbook
The 74F166 is a high speed 8-bit shift register that has fully synchronous serial parallel data entry selected by an active low parallel enable (PE) input. It also supports synchronous serial data input for easy expansion, clock enable for ”do nothing” mode, asynchronous master reset, and is expandable to 16 bits in 8-bit increments. The 74F166 has an industrial temperature range available (-40°C to +85°C).
PHILIPS 74F164 8-bit serial-in parallel-out shift register handbook
The 74F164 is an 8-bit edge-triggered shift register with serial data entry and an output from each of the eight stages
PHILIPS 74F160A* 74F161A 74F162A* 74F163A 4-bit binary counter handbook
The 74F161A, 74F163A 4-bit binary counters are produced by Philips Semiconductors. They feature synchronous counting and loading, two count enable inputs, positive edge-triggered clock, asynchronous master reset (74F161A) and synchronous reset (74F163A), high speed synchronous expansion, typical count rate of 130MHz and industrial range (-40°C to +85°C).
PHILIPS 74F157* 74F157A 74F158* 74F158A Data selectors/multiplexers handbook
This document introduces the features and parameters of the 74F157A / 74F158A data selectors / multiplexers. It is a high speed quad 2-input multiplexer which selects 4 bits of data from one of two sources under the control of a common select input (S). When E is high, all of the outputs (Yn) are forced low regardless of all other input conditions. Moving data from two registers to a common output bus is a common use of the 74F157A. The state of the select input determines the particular register from which the data comes. The device is the logic implementation of a 4-pole, 2-position switch where the position of the switch is determined by the logic levels supplied to the select input. The 74F158A is similar, but has inverting outputs (Yn).
PHILIPS 13 input NAND Gate FAST 74F133 handbook
The 74F133 is a 13-input NAND gate with a typical propagation delay of 4.0ns and a typical supply current of 2.0mA.
PHILIPS 74F138 1-of-8 decoder/demultiplexer handbook
The 74F138 is a 1-of-8 decoder/demultiplexer produced by Philips Semiconductors. It has demultiplexing capability, multiple input enable function, and is ideal for memory chip select decoding.
PHILIPS 74F14 Hex inverter Schmitt trigger handbook
The 74F14 is a six-inverter Schmitt trigger IC produced by Philips. It accepts standard TTL input signals and provides standard TTL output levels. It can transform slowly changing input signals into sharply defined, jitter-free output signals. In addition, it has greater noise margin than conventional inverters. Each circuit contains a Schmitt trigger followed by a Darlington level shifter and a phase splitter driving a TTL totem-pole output. The Schmitt trigger uses positive feedback to effectively speed-up slow input transitions, and provide different input threshold voltages for positive-going and negative-going input threshold (typically 800mV) is determined internally by resistor ratios and is insensitive to temperature and supply voltage variations.
PHILIPS 74F113 Dual J-K negative edge-triggered flip-flops without reset handbook
The 74F113 is a dual negative edge-triggered JK-type flip-flop manufactured by Philips Semiconductors. It features individual J, K, clock (CP), set (SD) inputs, true and complementary outputs. When the asynchronous SD input is low, it forces the outputs to the steady state levels shown in the function table, regardless of the level at the other inputs. When the clock (CP) input is high, the J and K inputs are enabled and data will be accepted. The logic levels at the J and K inputs may be allowed to change while the CP is high, and the flip-flop will perform according to the function table as long as minimum setup and hold times are observed. Output changes are initiated by the high-to-low transition of the CP.