Key facts
- Brand
- Altera
- Model
- MAX 3000A
- Category
- Other Electronics
- Documents
- 4
- Languages
- EN
- Last added
- 2012-08-06
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Altera MAX 3000A Programmable Logic Device Family Data Sheet
The document describes the MAX 3000A Programmable Logic Device (PLD) family, which consists of high-performance, low-cost CMOS EEPROM-based devices built on the Multiple Array Matrix (MAX) architecture. These devices offer high-density logic ranging from 600 to 5,000 usable gates and support 3.3-V in-system programmability (ISP) via the IEEE Std. 1149.1 JTAG interface.
Read onlineAltera MAX 3000A specifications
| Usable gates | 600 to 5,000 |
|---|---|
| Supply voltage | 3.3 V |
| Pin-to-pin logic delays | 4.5 ns |
| Counter frequencies | up to 227.3 MHz |
| I/O voltage compatibility | 5.0-V, 3.3-V, and 2.5-V |
| Reprogramming cycles | up to 100 times |
Source: Altera MAX 3000A Programmable Logic Device Family Data Sheet
All Altera MAX 3000A documents by type
Ratings, dimensions and ordering codes, for selection and design work.
Questions answered in these manuals
What is the maximum number of usable gates available in this device family?
The MAX 3000A devices offer high-density PLDs ranging from 600 to 5,000 usable gates.
From: Altera MAX 3000A Programmable Logic Device Family Data Sheet
What is the maximum counter frequency supported by these devices?
The devices support counter frequencies of up to 227.3 MHz.
From: Altera MAX 3000A Programmable Logic Device Family Data Sheet
What is the speed grade range for MAX 3000A devices?
The available speed grades are -4, -5, -6, -7, and -10.
From: Altera MAX 3000A Programmable Logic Device Family Data Sheet
What development software supports MAX 3000A?
Altera's development systems for Windows-based PCs, Sun SPARCstations, and HP 9000 Series workstations support these devices.
From: Altera MAX 3000A Programmable Logic Device Family Data Sheet
What is the maximum number of usable gates available in the MAX 3000A family?
The MAX 3000A family provides high-density PLDs ranging from 600 to 10,000 usable gates.
From: Altera MAX 3000A Programmable Logic Device Family Data Sheet
What is the fastest pin-to-pin logic delay specified for these devices?
The devices offer 4.5-ns pin-to-pin logic delays with counter frequencies of up to 227.3 MHz.
From: Altera MAX 3000A Programmable Logic Device Family Data Sheet