The document describes the MAX 9000 family of EEPROM-based programmable logic devices (EPLDs) built on Altera's third-generation MAX architecture. These high-density devices offer from 6,000 to 12,000 usable gates and support in-system programmability at 5.0V via the IEEE Std 1149.1 JTAG interface.
| Usable gates range | 6,000 to 12,000 |
|---|---|
| Pin-to-pin logic delays | 10 ns |
| Counter frequencies | up to 144 MHz |
| Programmable voltage interface | 3.3-V and 5.0-V |
| Program/erase cycles | 100 |
The devices support counter frequencies of up to 144 MHz.
Yes, the family offers 5.0-V in-system programmability through a built-in JTAG interface.