The MAX 9000 family consists of high-density, high-performance erasable programmable logic devices (EPLDs) based on Altera's third-generation MAX architecture. These CMOS-based devices offer 6,000 to 12,000 usable gates and support 5.0-V in-system programmability (ISP) via a built-in IEEE Std. 1149.1 JTAG interface. The family includes models ranging from the EPM9320 to the EPM9560, featuring speeds up to 144 MHz and compliance with the PCI Local Bus Specification, Revision 2.2.
| Usable gates | 6,000 to 12,000 |
|---|---|
| Logic delays | 10 ns |
| Counter frequencies | up to 144 MHz |
| Programmability | 5.0-V in-system programmability |
| Macrocells | 320 to 560 |
| Program/erase cycles | 100 |
| Power reduction | more than 50% |
The MAX 9000 family offers a -10 speed grade with pin-to-pin delays as fast as 10 ns.
Yes, the -10 speed grade of the MAX 9000 family is compliant with the PCI Local Bus Specification, Revision 2.2.
The MAX 9000 family is supported by Altera's MAX+PLUS II development system.