MAX 9000 Programmable Logic Device Family is a high-performance CMOS EEPROM-based programmable logic device (PLD) built on third-generation Multiple Array MatriX (MAX®) architecture.
The document describes the MAX 9000 family of high-density, high-performance erasable programmable logic devices (EPLDs) based on Altera's third-generation Multiple Array Matrix architecture. These CMOS-based devices offer up to 12,000 usable gates and support in-system programmability via a built-in IEEE Std. 1149.1 JTAG interface.
| Usable gates range | 6,000 to 12,000 |
|---|---|
| Pin-to-pin logic delays | 10 ns |
| Counter frequencies | up to 144 MHz |
| Programmability voltage | 5.0-V in-system programmability (ISP) |
| Programmable security | Yes |
The high-density EPLD family ranges from 6,000 to 12,000 usable gates.
MAX 9000 EPLDs are guaranteed for 100 program and erase cycles.
The devices support counter frequencies of up to 144 MHz.