The MAX 7000 is a high-performance EEPROM programmable logic device (PLD) produced by Altera Corporation. It is based on the second-generation MAX architecture. The MAX 7000 series devices have 5.0 V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface, and the ISP circuitry meets the IEEE Std. 1532 standard. The MAX 7000 series includes 5.0 V MAX 7000 devices and 5.0 V ISP based MAX 7000S devices. When the MAX 7000S device has 128 or more macrocells, it has an internal JTAG boundary scan test (BST) circuit. The MAX 7000 series devices have logic densities ranging from 600 to 5,000 usable gates, and have 5 ns pin-to-pin logic delays, which can achieve up to 175.4 MHz counter frequencies (including interconnect). PCI-compatible devices are available.
The document is a datasheet for the Altera MAX 7000 Programmable Logic Device Family. It describes high-density, high-performance PLDs based on second-generation MAX architecture, fabricated with advanced CMOS technology. The family includes standard devices and enhanced versions (MAX 7000E) as well as in-system programmable variants (MAX 7000S).
| Usable gates range | 600 to 5,000 usable gates |
|---|---|
| Macrocells range | 32 to 256 macrocells |
| Pin-to-pin logic delays | as fast as 5 ns |
| Counter frequencies | up to 175.4-MHz |
| Programming cycles | up to 100 times |
The MAX 7000 family provides logic densities ranging from 600 to 5,000 usable gates.
The devices offer 5-ns pin-to-pin logic delays.
The devices can be programmed and erased up to 100 times.