Altera Cyclone EP1C FPGA Family Data Sheet

About this manual

This document is a preliminary data sheet for the Altera Cyclone field programmable gate array (FPGA) family. It describes the architecture based on a 1.5-V, 0.13-µm SRAM process and lists device densities ranging from 2,910 to 20,060 logic elements.

The text provides detailed specifications for various models including EP1C3, EP1C4, EP1C6, EP1C12, and EP1C20. Key features covered include embedded M4K RAM blocks, phase-locked loops (PLLs), support for LVDS and PCI standards, and available package options such as QFP and FineLine BGA.

What's inside

• Introduction
• Features
• Functional Description
• Logic Array Blocks
• Embedded Memory
• Global Clock Network & Phase-Locked Loops
• Power Consumption
• Timing Model
• Device Pin-Outs
• Ordering Information

Specifications

Frequently asked questions

What is the process technology used for Cyclone FPGAs?

Cyclone devices are based on a 1.5-V, 0.13-µm, all-layer copper SRAM process.

What are the logic element densities available in the Cyclone family?

The family offers densities ranging from 2,910 to 20,060 logic elements.

Which design software supports Cyclone devices?

Cyclone devices are supported by the Altera Quartus II design software.