This document describes the features of the 74HC/HCT595 integrated circuit, including 8-bit serial input, 8-bit serial or parallel output, storage register with 3-state outputs, shift register with direct clear, and a shift out frequency of 100 MHz (typ).
The 74HC/HCT595 is a high-speed Si-gate CMOS device that is pin compatible with low power Schottky TTL (LSTTL). It functions as an 8-stage serial shift register with a storage register and 3-state outputs, specified in compliance with JEDEC standard no. 7A. The device features separate clocks for the shift and storage registers, allowing data to be shifted on the positive-going transitions of the SH CP input and transferred to the storage register on the ST CP input. It includes an asynchronous reset (active LOW) for all 8 shift register stages and 8 parallel 3-state bus driver outputs controlled by an output enable input.
| Shift register stages | 8-stage |
|---|---|
| Maximum clock frequency (HC) | 100 MHz |
| Output capability | Parallel outputs; bus driver; serial output; standard |
Data is transferred to the storage register on a positive-going transition of the ST CP input.
When the output enable input is HIGH, the parallel outputs enter a high-impedance OFF-state.