The K4S560432E / K4S560832E / K4S561632E is a 268,435,456 bit synchronous high data rate Dynamic RAM organized as 4 x 16,785,216 / 4 x 8,392,608 / 4 x 4,196,304 words by 4bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth applications.
The document provides a complete specification for Samsung's 256 Mb E‑die SDRAM family in x4, x8 and x16 configurations. It includes part numbers, memory organization, package details, electrical characteristics, and timing parameters.
Key features include JEDEC‑compliant 3.3 V operation, LVTTL interface, up to 133 MHz clock speed, multiple burst lengths, and support for auto and self‑refresh. Absolute maximum ratings and recommended operating conditions are listed for reliable design.
| Memory organization | 64M × 4, 32M × 8, 16M × 16 |
|---|---|
| Maximum clock frequency | 133 MHz |
| Interface | LVTTL |
| Supply voltage (VDD, VDDQ) | 3.0 V – 3.6 V (typical 3.3 V) |
| Operating temperature range | -55 °C to +150 °C |
| CAS latency | 2 or 3 |
| Burst length | 1, 2, 4, 8, Full page |
| Refresh period | 64 ms (8K cycles) |
| Input logic high voltage (VIH) | 2.0 V – 3.0 V |
| Input logic low voltage (VIL) | -0.3 V – 0.8 V |
| Output logic high voltage (VOH) | 2.4 V |
| Output logic low voltage (VOL) | 0.4 V |
The recommended supply voltage is 3.3 V, with a permissible range from 3.0 V to 3.6 V.
It can operate from –55 °C up to +150 °C.
The device is offered in 64 M × 4, 32 M × 8, and 16 M × 16 organizations.
The SDRAM supports up to 133 MHz operation.