The Samsung 256 Mb E‑die CMOS SDRAM family provides high‑performance memory organized in four banks with configurable data widths (x4, x8, x16). Features include JEDEC‑standard 3.3 V operation, LVTTL‑compatible address multiplexing, selectable CAS latency, and programmable burst lengths.
The datasheet contains revision history, functional block diagrams, pin configurations, absolute maximum ratings, recommended operating conditions, capacitance values, and a simplified truth table for command decoding. It also lists ordering information, package dimensions (54‑pin TSOP), and detailed electrical characteristics for each supported part number.
| Organization | 16M × 4 Bit × 4 Banks / 8M × 8 Bit × 4 Banks / 4M × 16 Bit × 4 Banks |
|---|---|
| Supply Voltage (VDD, VDDQ) | 3.0 V – 3.6 V (typ. 3.3 V) |
| Maximum Operating Frequency | 133 MHz (CL = 3) for x4/x8 parts, 166 MHz (CL = 3) for x16 part |
| Package Type | 54‑pin TSOP |
| Storage Temperature Range | -55 °C to +150 °C |
| Refresh Period | 64 ms (8K cycles) |
| CAS Latency Options | 2 or 3 |
| Burst Length Options | 1, 2, 4, 8, Full page |
The device operates from 3.0 V to 3.6 V, with a typical value of 3.3 V.
The x4 and x8 parts run up to 133 MHz, while the x16 part can operate up to 166 MHz.
All parts are supplied in a 54‑pin TSOP package.
The SDRAM can be stored from –55 °C up to +150 °C.