Micron 128Mb DDR SDRAM (x4, x8, x16) Datasheet

About this manual

The Micron 128 Mb DDR SDRAM is a high‑speed CMOS dynamic RAM organized as a quad‑bank memory with capacities of 32 Mbit x4, 16 Mbit x8 or 8 Mbit x16. It uses a double‑data‑rate architecture with a bidirectional data strobe (DQS) and differential clock inputs (CK and CK#) to achieve two data transfers per clock cycle.

The device is supplied in a 66‑pin plastic TSOP package, operates from a 2.5 V I/O supply (SSTL_2 compatible), and supports programmable burst lengths of 2, 4 or 8. Features include auto‑precharge, auto‑refresh, self‑refresh, and low‑power options.

What's inside

• Functional Block Diagram
• Pin Descriptions
• Functional Description
• Mode Register
• Commands
• Operation
• Operating Conditions
• Absolute Maximum Ratings
• Voltage and Timing Waveforms
• Timing Parameters

Specifications

Frequently asked questions

What supply voltage does the Micron DDR SDRAM require?

The device uses a Vpp of +2.5 V + 0.2 V and a VopQ of +2.5 V.

What package type is the 128 Mb DDR SDRAM available in?

It is supplied in a 66‑pin plastic TSOP package (400 mil width, 0.65 mm pitch).

What are the supported burst lengths for this DDR SDRAM?

The memory supports programmable burst lengths of 2, 4, or 8.

What is the cycle time at CL = 2?

The minimum cycle time is 7.5 ns at CL = 2 (DDR266B).