This document describes the configuration and characteristics of Micron Technology, Inc.'s 64Mb x4, x8, x16 SDRAM products, including refresh count, row addressing, column addressing, bank addressing, etc. The product adopts synchronous DRAM technology, complies with PC66, PC100, and PC133 standards, and has features such as internal pipelined operation and programmable burst lengths.
The MT48LC16M4A2 is a 64 Mb synchronous DRAM offered by Micron. It is organized as quad‑bank memory with three density options: 16 Meg × 4, 8 Meg × 8, and 4 Meg × 16, each using a 54‑pin TSOP II package. The device operates from a single +3.3 V supply and supports commercial (0 °C to +70 °C) and extended (‑40 °C to +85 °C) temperature ranges.
Key features include fully synchronous operation with all signals registered on the positive clock edge, programmable burst lengths (1, 2, 4, 8, or full‑page), auto‑precharge, auto‑refresh, self‑refresh (standard and low‑power), and LVTTL‑compatible I/O. Timing parameters allow operation up to 143 MHz with CAS latencies of 2 or 3 cycles.
| Capacity | 64 Mb |
|---|---|
| Density Options | 16 Meg × 4, 8 Meg × 8, 4 Meg × 16 |
| Burst Length Options | 1, 2, 4, 8, full‑page |
Burst lengths of 1, 2, 4, 8, or a full‑page burst can be selected.