This document is a technical data sheet about the 16Mb x16 SDRAM product produced by Micron Technology. The product features PC100 functionality, fully synchronous operation, and internal bank and column addressing.
The Micron MT48LC1M16A1 is a 16 Mb (1 Meg × 16) synchronous DRAM organized as two 512 K × 16 banks. It operates from a single +3.3 V + 0.3 V supply and features LVTTL‑compatible I/O. The device supports programmable burst lengths of 1, 2, 4, 8 or a full page and CAS latencies of 1, 2 or 3 clock cycles.
The datasheet provides a functional block diagram, pin descriptions for the 50‑pin TSOP package, detailed command timing, mode register definitions, and electrical characteristics such as maximum ratings and timing parameters for speeds up to 166 MHz (6 ns).
| Capacity | 16 Mb (1 Meg × 16) |
|---|---|
| Organization | 512 K × 16 × 2 banks |
| Supply Voltage | +3.3 V + 0.3 V |
| CAS Latency | 1, 2, 3 clocks |
| Burst Lengths | 1, 2, 4, 8, full page |
| Package | 50‑Pin TSOP (400 mil) TG |
| Maximum Clock Speed | 166 MHz (6 ns) |
| I/O Compatibility | LVTTL‑compatible inputs and outputs |
It operates from a single +3.3 V + 0.3 V power supply.
The device supports CAS latencies of 1, 2, or 3 clock cycles.
Programmable burst lengths are 1, 2, 4, 8 or a full‑page burst.
It is supplied in a 50‑pin TSOP (400 mil) TG package.