This document introduces the features and characteristics of the 16Mb (x4/x8) SDRAM product from Micron, including PC100-compliant, fully synchronous, internal pipelined operation, and programmable burst lengths.
The Micron 16 Mb SDRAM is a high‑speed synchronous DRAM offered in 4 Meg×4 and 2 Meg×8 configurations. It operates at 3.3 V with LVTTL‑compatible I/O and includes features such as concurrent auto‑precharge, self‑refresh and programmable burst lengths.
The document provides functional block diagrams, pin descriptions, timing parameters, and detailed operation modes including initialization, mode register programming, and power‑down states. It also lists absolute maximum ratings and package dimensions for the 44‑pin TSOP package.
| Organization | 4 Meg×4 (2 Meg×4×2 banks) or 2 Meg×8 (1 Meg×8×2 banks) |
|---|---|
| Supply Voltage | +3.3 V, +0.3 V |
| I/O Standard | LVTTL‑compatible |
| Refresh Interval | 64 ms, 4,096‑cycle refresh |
| Burst Lengths | 1, 2, 4, 8, full page |
| Maximum Clock Frequency | 125 MHz |
| Package | 44‑pin TSOP (400 mil) |
It uses a single +3.3 V supply with an additional +0.3 V bias.
The device supports programmable burst lengths of 1, 2, 4, 8, or a full‑page burst.
Each bank has 2,048 rows and either 1,024 columns (x4 version) or 512 columns (x8 version).