256Mb: x4, x8, x16 DDR333 SDRAM technical specifications
The DDR333 SDRAM is a high‑speed CMOS dynamic RAM operating at 167 MHz with a peak data rate of 333 Mb/s per pin. It is offered in 256 Mb densities with data‑width options of x4, x8, and x16, and is backward compatible with DDR200 and DDR266 designs.
The addendum details the two package options—66‑pin TSOP and 60‑ball FBGA—along with full pin‑out tables, timing parameters, capacitance values, and recommended operating conditions for designers integrating these parts into memory subsystems.
| Clock frequency | 167 MHz |
|---|---|
| Data rate | 333 Mb/s per pin |
| Core voltage | +2.5 V ±0.2 V |
| Package types | 66‑pin TSOP, 60‑ball FBGA |
| Package types (cont.) | 60‑ball FBGA (16 × 9 mm) |
| Cycle time (CL = 2.5) | 6 ns |
| Average refresh interval | 7.8 µs |
The device is offered in 256 Mb densities with x4, x8, and x16 data‑width configurations.
It is available in a 66‑pin TSOP package and a 60‑ball FBGA package.
The part operates at a 167 MHz clock frequency, providing a 333 Mb/s per pin data rate.