This document describes the features and characteristics of Micron's 128Mb x32 DDR SDRAM product, including voltage, data transfer rate, data storage structure, clock inputs, etc.
The MT46V4M32 is a 128‑Mb (x32) DDR SDRAM that uses a double‑data‑rate, 2n‑prefetch architecture to achieve high‑speed operation. It is internally organized as a quad‑bank DRAM and contains 134,217,728 bits of CMOS dynamic memory.
The datasheet describes the functional block diagram, pin descriptions for 100‑pin TQFP and 144‑ball FBGA packages, initialization sequence, mode register settings, burst length options, timing parameters up to 300 MHz, and electrical characteristics such as a 2.5 V I/O supply and optional 1.8 V VppQ option.
| Capacity | 128 Mb (x32) |
|---|---|
| Organization | 1 Meg × 32 × 4 banks |
| Supply Voltage (Vop) | +2.5 V ±0.125 V |
| I/O Standard | SSTL_2 compatible (2.5 V) |
| Maximum Clock Frequency | 300 MHz (CL=5) |
| Burst Lengths | 2, 4, 8, or full page |
| Auto‑Refresh Interval | 32 ms, 4,096‑cycle |
It provides 128 Mb organized as a 32‑bit wide device.
The device supports programmable burst lengths of 2, 4, 8, or a full‑page burst.
The core Vop supply is +2.5 V with a ±0.125 V tolerance, and the I/O is SSTL_2 compatible.