Industrial

The SN74F112 is a dual negative-edge-triggered J-K flip-flop with clear and preset functions. It contains two independent J-K flip-flops. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. Data at the J and K inputs meeting the setup time requirements is transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. The SN74F112 can perform as a toggle flip-flop by tying J and K high. The device is characterized for operation from 0°C to 70°C.

SN74LVC112A is a dual negative-edge-triggered J-K flip-flop with clear and preset functions. It operates from 1.65V to 3.6V and accepts input voltages up to 5.5V. It has a fast propagation delay and stable output levels. Can be used as a flip-flop or toggle flip-flop.

The document describes the features and characteristics of Harris Semiconductor SCHS139D, including hysteresis on clock inputs for improved noise immunity and increased input rise and fall times, asynchronous reset, complementary outputs, buffered inputs, wide operating temperature range, balanced propagation delay and transition times, etc.

CD54AC112, CD74AC112 is a dual J-K negative-edge-triggered flip-flop with clear and preset functions from Texas Instruments.

The document contains information about several orderable devices, including their models, package types, pin count, package quantity, and other characteristics.

CD4027B is a four-bit exclusive OR gate produced by Texas Instruments. It has 16 pins and is available in ceramic dual in-line, plastic dual in-line, small outline and thin shrink small outline packages.

The MC74HC273A/D is an Onsemi high-performance silicon-gate CMOS octal D flip-flop with common clock and reset. Its pinout is identical to that of the LS273. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of eight D flip-flops with common Clock and Reset inputs. Each flip-flop is loaded with a low-to-high transition of the Clock input. Reset is asynchronous and active low.

SN54ACT374, SN74ACT374 are two 8-bit D-type edge-triggered flip-flops, their output pins are designed with 3-state output, which makes them very suitable for driving high-capacitance or relatively low-impedance loads.

This document describes a CMOS device with enhanced performance, which contains two independent positive-edge-triggered D-type flip-flops. It features low power consumption and high-speed switching noise suppression.

This document describes the features and characteristics of the SN74AUC1G80 single positive-edge-triggered D-type flip-flop. The flip-flop is designed for operation at 1.65V to 1.95V and features low power consumption, high output drive capability, and noise immunity.

M74HC374 is a high-speed CMOS OCTAL D-TYPE FLIP FLOP WITH 3-STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate C2MOS technology. This 8 bit D-TYPE FLIP FLOP is controlled by a clock input (CK) and an output enable input (OE). On the positive transition of the clock, the Q outputs will be set to the logic state that were setup at the D inputs. While the OE input is at low level, the eight outputs will be in a normal logic state (high or low logic level) and while OE is high the outputs will be in a high impedance state. The output control does not affect the internal operation of flip-flops; that is, the old data can be retained or the new data can be entered even while the outputs are off. All inputs are equipped with protection circuits against static discharge and transient excess voltage.

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The SY10/100EL52 is a differential data, differential clock D flip-flop. These devices have higher performance capabilities than the E452 devices, with faster propagation delays and output transition times. They are ideally suited for applications that require the ultimate in AC performance. The EL52 can be used as a negative edge triggered device with its differential clock inputs.

The MC10EP/100EP52 is a differential data, differential clock D flip-flop. The device is pin and functionally equivalent to the EL52 device. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP52 allow the device to also be used as a negative edge triggered device. The EP52 employs input clamping circuitry so that under open input conditions (pulled down to VEE) the outputs of the device will remain stable. The 100 Series contains temperature compensation. Features: 330 ps Typical Propagation Delay, Maximum Frequency - 4 GHz Typical, PECL Mode: VCC = 3.0 V to 5.5 V with VEE = 0 V, NECL Mode: VCC = 0 V with VEE = -3.0 V to -5.5 V, Open Input Default State, Safety Clamp on Inputs, Q Output Will Default LOW with Inputs Open or at VEE, Pb-Free Packages are Available.

SN54LV273A/SN74LV273A are 8-bit D flip-flops designed for 2-V to 5.5-V VCC operation.