CDC2510C is a 3.3V low-skew, low-jitter, phase-lock loop (PLL) clock driver released by TI. It uses a PLL to precisely align the feedback output (FBOUT) with the clock input (CLK) signal in both frequency and phase. It is specifically designed for use with synchronous DRAMs. The CDC2510C operates at VCC = 3.3 V. It also provides integrated series damping resistors, making it ideal for driving point-to-point loads. One bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. All outputs can be enabled or disabled through a single output enable input. When the G input is high, all outputs are enabled.
The CDC2510C is a high-performance, low-skew, low-jitter phase-lock loop (PLL) clock driver designed specifically for use with synchronous DRAMs. It operates at 3.3 V and provides integrated series-damping resistors, making it ideal for driving point-to-point loads without requiring external RC networks. The device distributes one clock input to a bank of ten outputs, adjusting the output signal duty cycles to 50 percent independently of the input duty cycle.
| Operating Voltage | 3 V to 3.6 V |
|---|---|
| Operating Temperature | 0°C to 85°C |
| Clock Frequency | 25 MHz to 125 MHz |
| Phase Error (Static) | +/- 150 ps |
| Jitter | 100 ps |
| Output Skew | 200 ps |
| Output Duty Cycle | 45% to 55% |
No, the CDC2510C does not require external RC networks because the loop filter for the PLL is included on-chip.
The stabilization time is 1/10 ms, required for the PLL to phase lock the feedback signal to the reference signal.
Yes, the PLL can be bypassed for test purposes by strapping AVcc to ground.