18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL™ Architecture CY7C1370DV25 CY7C1372DV25 is a high-performance SRAM produced by CYPRESS. It has the characteristics of full synchronization, pipeline, burst operation, and zero wait state.
The CY7C1370DV25 and CY7C1372DV25 are 2.5V, 512K x 36 and 1 Mbit x 18 synchronous pipelined burst SRAMs with No Bus Latency (NoBL) logic. They are designed to support unlimited true back-to-back Read/Write operations with no wait states, transferring data on every clock cycle. These devices feature internally self-timed output buffer control and are pin-compatible and functionally equivalent to ZBT devices.
| Maximum Access Time (250 MHz) | 2.6 ns |
|---|---|
| Maximum Access Time (200 MHz) | 3.0 ns |
| Maximum Access Time (167 MHz) | 3.4 ns |
| Maximum Operating Current (250 MHz) | 350 mA |
| Maximum CMOS Standby Current | 70 mA |
| Core Power Supply | 2.5V |
The devices support 250-MHz bus operations with zero wait states.
The maximum operating current is 350 mA.
The maximum access time is 3.4 ns.
The CY7C1370DV25 has 36 data I/O lines.