Cypress CY7B993V/CY7B994V High-speed Multi-phase PLL Clock Buffer Datasheet

This data sheet provides a detailed overview of the Cypress CY7B993V and CY7B994V high-performance multi-phase PLL clock buffers.


Cypress CY7B993V/CY7B994V High-speed Multi-phase PLL Clock Buffer Datasheet - cover page
Brand
Cypress
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
15
File format
PDF
File size
390 KB
Published
12 June, 2012
Updated
30 September, 2023
MD5 checksum
1B3BF7ED6DED5BB0302931F6465D43AE

About this manual

The Cypress CY7B993V and CY7B994V are High-speed Multi-phase PLL Clock Buffers that offer user-selectable control over system clock input/output operations. These devices feature a guaranteed maximum Total Timing Budget (TTB) window, specifying all occurrences of output clocks with respect to the input reference clock across variations in output frequency, supply voltage, operating temperature, input edge rate, and process.

What's inside

  • Features
  • Functional Description
  • Pin Definitions
  • Block Diagram Description
  • Package Information

Specifications

Max Total Timing Budget (TTB) window500-ps
Output skew< 200 ps
Supply voltage3.3V
Operating temperature rangesCommercial, Industrial

Frequently asked questions

What is the maximum total timing budget window for these devices?

The CY7B993V and CY7B994V offer a guaranteed maximum Total Timing Budget (TTB) window of 500 ps.

What is the frequency range for the CY7B994V model?

The CY7B994V High-speed Multi-phase PLL Clock Buffer operates at frequencies from 24 MHz to 200 MHz.

How many outputs can drive terminated lines at 200 MHz in commercial temperature?

The device features sixteen outputs capable of driving terminated lines at a frequency of 200 MHz.

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