Cypress Manuals

This document describes the features and characteristics of the enCoRe™ USB CY7C63221/31A product produced by Cypress Semiconductor Corporation.

The CY7C197 is a high-performance CMOS static RAM organized as 256K words by 1 bit. It features high speed, low power consumption, and automatic power-down.

CY7C182 is a high-performance CMOS static RAM from Cypress Semiconductor Corporation. It features high speed, low power consumption, TTL-compatible inputs and outputs. It is ideal for cache memory applications.

8Kx9 Static RAM CY7C182 is a high-speed CMOS static RAM organized as 8192 * 9 bits, produced by Cypress Semiconductor Corporation. It features 25ns of fast access time and a maximum power consumption of 770mW. In addition, the product also has an automatic power-down feature and easy memory expansion.

The CY7C1354B and CY7C1356B are 3.3V, 256K x 36 and 512K x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1354B and CY7C1356B are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature is very impressive.

The CY62138CV25/30/33 and CY62138CV are high-performance CMOS static RAMs organized as 256K words by eight bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications. The device can be put into standby mode reducing power consumption by more than 99% when deselected (CE1 HIGH or CE2 LOW).

The CY2SSTV8575 is a high-performance, low-skew, low jitter zero-delay buffer designed to distribute differential clocks in high-speed applications. It generates five differential pair clock outputs from one differential pair clock input, and features differential feedback clock outputs and inputs. It supports an operating frequency of 60 MHz to 170 MHz, and is compatible with 266 MHz DDR SDRAM. It has low jitter (cycle-to-cycle) and very low skew, and supports spread spectrum. It also has a power management control input, high-impedance outputs when the input clock is less than 20 MHz, and operates at 2.5V.

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This datasheet provides detailed information on the features and characteristics of the CY7C4255/65 8K/16Kx18 deep synchronous FIFOs

This datasheet introduces the features of Cypress Semiconductor's 3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO w/ Bus Matching CY7C43644AV/CY7C43664AV/CY7C43684AV.

CY7C1381C/CY7C1383C is a 3.3V synchronous flow-through SRAM designed to interface with high-speed microprocessors with minimum glue logic. It features support for 133-MHz bus operations, 512K x 36 and 1M x 18 common I/O, high-performance access rate, and more.

Cypress Ultra37000 family of high-performance CPLDs is a high-density programmable logic solution with 32 to 512 macrocells, 32 to 264 I/O pins and five dedicated inputs, including four clock pins.

This document introduces the features and characteristics of the Cypress Ultra37000 CPLD family of products, including high density, simple timing model, 3.3V and 5V versions, PCI compatibility, programmable bus hold capabilities, intelligent product term allocator, flexible clocking, consistent packaging/pinout offering, etc.

The Ultra37000™ family of CMOS CPLDs provides a range of high-density programmable logic solutions with unparalleled system performance. The family includes 5V and 3.3V versions, and supports PCI compatibility.