The DS90CF581 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 40 MHz, 24 bits of RGB data and 4 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY, CNTL) are transmitted at a rate of 280 Mbps per LVDS data channel. Using a 40 MHz clock, the data throughput is 140 Megabytes per second. This transmitter is intended to interface to any of the FPD Link receivers. The chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.
The DS90CF581 is a transmitter designed to convert 28 bits of CMOS/TTL data into four LVDS data streams, transmitting 24 bits of RGB data and 4 bits of LCD timing/control data. It operates at a transmit clock frequency of 40 MHz, achieving a data throughput of 140 Megabytes per second.
| Data Throughput | 140 Megabytes per second |
|---|---|
| Supply Voltage | 4.5 to 5.5 V |
| Package Type | 56-lead TSSOP |
| LVDS Output Swing | 290 mV |
The maximum transmit clock frequency is 40 MHz.
No, the PLL requires no external components.
The transmitter supply current in power-down mode is 1 mA.