DS90CF563/DS90CF564 LVDS 18-Bit Color Flat Panel Display (FPD) Link— 65 MHz. The product converts 21 bits of CMOS/TTL data into three LVDS data streams and parallel transmits a phase-locked transmit clock and data streams over a fourth LVDS link. At a transmit clock frequency of 65 MHz, 21 bits of input data are sampled and transmitted every cycle of the transmit clock. With a 65 MHz clock, the data throughput is 171 MB/s. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.
The document describes a chipset consisting of the DS90CF563 transmitter and DS90CF564 receiver designed for LVDS (Low Voltage Differential Signaling) interfaces. The system converts 21 bits of CMOS/TTL data into three LVDS data streams plus a phase-locked transmit clock, operating at frequencies up to 65 MHz.
| Clock Frequency Support | 20 to 65 MHz |
|---|---|
| Data Bandwidth | Up to 171 Mbytes/s |
| LVDS Swing | 290 mV typ |
| Supply Voltage (Vcc) | 4.75 to 5.25 V |
| Operating Temperature Range | -10°C to +70°C |
| Package Type | 48-lead TSSOP |
The device supports shift clocks from 20 to 65 MHz.
Using a 65 MHz clock, the data throughput is 171 Mbytes per second.
No, the PLL requires no external components.