This document describes the features and characteristics of the IDT23S05 3.3V Zero Delay Clock Buffer, including phase-lock loop clock distribution, 10MHz to 133MHz operating frequency, five outputs, low jitter, and zero input-output delay.
The IDT23S05 is an 8-pin high-speed phase-lock loop (PLL) clock buffer designed to address high-speed clock distribution applications. It accepts one reference input and drives five low skew clocks, operating within a frequency range of 10 to 133MHz. The device achieves zero delay by aligning the phase between the incoming clock and the output clock.
| Supply Voltage | 3.3V |
|---|---|
| Output Skew | < 250ps |
| Jitter (Cycle-to-Cycle) | < 200 ps |
| Package Type | 8-pin SOIC |
The device operates up to a maximum frequency of 133MHz.
No, the device does not require an external RC network as it has on-chip PLLs.