ispLSI ® 1024/883 is a high-density PLD with 4000 PLD gates, 48 I/O pins, six dedicated inputs, 144 registers, and can be used for fast counters, state machines, address decoders, etc.
The ispLSI 1024/883 is a high‑density, in‑system programmable logic device built to MIL‑STD‑883 specifications. It offers 4000 PLD gates, 48 universal I/O pins, six dedicated inputs, four dedicated clock pins, 144 registers, and a global routing pool for full interconnectivity. The device supports 5‑V ISP programming, non‑volatile reprogrammability, and includes security features to prevent unauthorized copying.
The document contains detailed functional block diagrams, absolute maximum ratings, recommended operating conditions, extensive timing parameters (external and internal), pin‑out diagrams, and ordering information. Technical tables list electrical characteristics, capacitance values, data retention, and erase/reprogram cycle limits, enabling designers to integrate the part into their systems.
| Maximum Operating Frequency | 60 MHz |
|---|---|
| Propagation Delay (tod) | 20 ns |
| Number of I/O Pins | 48 universal I/O pins (plus 6 dedicated inputs) |
| Number of Registers | 144 |
| Data Retention | 20 years |
| Erase/Reprogram Cycles | 10 000 cycles |
The device can operate up to 60 MHz.
It provides 48 universal I/O pins and six dedicated input pins.