ispLSI® 1024EA is a high density programmable logic device from Infineon with 4000 PLD gates and 48 I/O pins, supports IEEE 1149.1 boundary scan testing, and can be programmed in-system.
The ispLSI 1024EA is a high‑density, in‑system programmable PLD from Lattice Semiconductor. It offers 4000 logic gates, 48 universal I/O pins, four dedicated clock pins, and a global routing pool for flexible interconnectivity. The device supports both 3.3 V and 5 V I/O, open‑drain outputs, and is fully IEEE 1149.1 JTAG testable.
Key specifications include a maximum operating frequency of 200 MHz, a typical propagation delay of 4.5 ns, and a 100‑pin TQFP package. Electrical characteristics such as supply voltage (4.75‑5.25 V), input low voltage (0‑0.8 V), and output drive capabilities (4 mA source, 8 mA sink) are provided, along with detailed timing parameters for the global routing pool, logic blocks, and clock distribution network.
| Logic gates | 4000 PLD gates |
|---|---|
| I/O pins | 48 universal I/O pins, 2 dedicated inputs |
| Maximum operating frequency | 200 MHz |
| Propagation delay | 4.5 ns |
| Input low voltage (VIL) | 0 V – 0.8 V |
| Package | 100‑Pin TQFP |
| Open‑drain output option | Supported |
The device can operate up to 200 MHz.
It provides 48 universal I/O pins plus two dedicated input pins.
Yes, the outputs can be programmed as open‑drain.
The device is offered in a 100‑Pin TQFP package.