Update: 29 September, 2023
The ispClock 5600 family is an in-system programmable, zero-delay clock generator with a universal fan-out buffer. It operates in the range of 10MHz to 320MHz and offers low output to output skew (<50ps) and low jitter peak-to-peak (<60ps). It has up to 20 programmable fan-out buffers with various programmable features such as output standards, output impedance, slew rate, and individual enable controls. The family also includes a fully integrated high-performance PLL with programmable lock detect and multiply/divide ratio control. It supports precision programmable phase adjustment per output, up to five clock frequency domains, and flexible clock reference and external feedback inputs.
File format: PDF
Size: -
MD5 Checksum: 7E470ED3960C6E01C2097BC8F65F383D
Publication date: 11 May, 2012
Downloads: -
PDF Link: Lattice ispClock 5600 Family handbook PDF