The ispClock 5600 family is an in-system programmable, zero-delay clock generator with a universal fan-out buffer. It operates in the range of 10MHz to 320MHz and offers low output to output skew (<50ps) and low jitter peak-to-peak (<60ps). It has up to 20 programmable fan-out buffers with various programmable features such as output standards, output impedance, slew rate, and individual enable controls. The family also includes a fully integrated high-performance PLL with programmable lock detect and multiply/divide ratio control. It supports precision programmable phase adjustment per output, up to five clock frequency domains, and flexible clock reference and external feedback inputs.
The ispClock5600 family provides in‑system programmable, zero‑delay clock generators with up to five clock frequency domains and configurable fan‑out buffers. Devices support a wide range of I/O standards (LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL) and offer programmable input, feedback and output dividers for flexible frequency synthesis.
The family includes the ispClock5610 (10 single‑ended/5 differential outputs) and ispClock5620 (20 single‑ended/10 differential outputs). Detailed electrical specifications, absolute maximum ratings, and recommended operating conditions are provided for both commercial (0 °C‑70 °C) and industrial (‑40 °C‑85 °C) temperature ranges.