Key facts
- Brand
- Lattice
- Model
- ispLSI 1024
- Category
- Other Electronics
- Documents
- 2
- Languages
- EN
- Last added
- 2012-05-11
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Lattice ispLSI 1024EA High Density PLD Datasheet
The ispLSI 1024EA is a high‑density, in‑system programmable PLD from Lattice Semiconductor. It offers 4000 logic gates, 48 universal I/O pins, four dedicated clock pins, and a global routing pool for flexible interconnectivity. The device supports both 3.3 V and 5 V I/O, open‑drain outputs, and is fully IEEE 1149.1 JTAG testable.
Key specifications include a maximum operating frequency of 200 MHz, a typical propagation delay of 4.5 ns, and a 100‑pin TQFP package. Electrical characteristics such as supply voltage (4.75‑5.25 V), input low voltage (0‑0.8 V), and output drive capabilities (4 mA source, 8 mA sink) are provided, along with detailed timing parameters for the global routing pool, logic blocks, and clock distribution network.
Lattice ispLSI 1024 specifications
| Logic gates | 4000 PLD gates |
|---|---|
| I/O pins | 48 universal I/O pins, 2 dedicated inputs |
| Maximum operating frequency | 200 MHz |
| Propagation delay | 4.5 ns |
| Input low voltage (VIL) | 0 V – 0.8 V |
| Package | 100‑Pin TQFP |
| Open‑drain output option | Supported |
All Lattice ispLSI 1024 documents by type
Ratings, dimensions and ordering codes, for selection and design work.
Questions answered in these manuals
What is the maximum operating frequency of the ispLSI 1024EA?
The device can operate up to 200 MHz.
How many I/O pins does the ispLSI 1024EA provide?
It provides 48 universal I/O pins plus two dedicated input pins.
What is the maximum operating frequency of the ispLSI 1024/883?
The device can operate up to 60 MHz.
How many I/O pins does the ispLSI 1024/883 provide?
It provides 48 universal I/O pins and six dedicated input pins.