This document introduces the features and characteristics of the high-performance EE CMOS programmable logic of the MACH 1 and 2 CPLD families.
The MACH 1 & 2 families from Lattice provide high‑performance, low‑cost Complex Programmable Logic Devices (CPLDs) with 32 to 128 macrocells and 44‑100 pins in PLCC, PQFP and TQFP packages. Features include SpeedLocking™ fixed timing, Bus‑Friendly I/Os, JTAG‑compatible in‑system programming, and PCI compliance.
Supported by Lattice/Vantis DesignDirect software, the devices offer configurable macrocells, programmable power‑down mode (up to 75 % savings), and a range of commercial and industrial speed grades from 5 ns to 18 ns tpp.
| Macrocells | 32 to 128 |
|---|---|
| Pin count | 44 to 100 pins |
| Commercial tpp speed grades | 5, 5.5, 6, 7.5, 10, 12, 15 ns |
| Industrial tpp speed grades | 7.5, 10, 12, 14, 18 ns |
| Power‑down savings | up to 75 % |
| Programming interface | JTAG (IEEE 1149.1)‑compatible, 5‑V in‑system programming |
| PCI compliance | Yes |
| SpeedLocking™ | Guaranteed fixed timing up to 16 product terms |
The devices support JTAG (IEEE 1149.1)‑compatible, 5‑V in‑system programming.
Commercial speed grades range from 5 ns to 15 ns tpp (5, 5.5, 6, 7.5, 10, 12, 15 ns).
MACH devices are offered with 32, 64, 96 or 128 macrocells.
A programmable power‑down mode provides power savings of up to 75 %.