This document describes the features and characteristics of the ispLSI ® 1048E high-density programmable logic chip, including high-density programmable logic, high-performance E2CMOS® technology, and in-system programmability.
The Lattice ispLSI 1048E is a high‑density programmable logic device (PLD) that integrates 8 000 PLD gates, 96 universal I/O pins, twelve dedicated inputs and four dedicated clock inputs. It provides 288 internal registers and a global routing pool for flexible interconnectivity, supporting both combinatorial and registered logic functions.
Key features include 5 V in‑system programmability, non‑volatile re‑programming, TTL‑compatible I/O, and high‑speed operation up to 125 MHz. The device is suited for digital logic design, fast counters, state machines, address decoders and other applications requiring dense logic and flexible pin placement.
| Logic Gates | 8,000 PLD gates |
|---|---|
| I/O Pins | 96 universal I/O pins |
| Registers | 288 registers |
| Maximum Operating Frequency | 125 MHz |
| Propagation Delay | 7.5 ns |
| Supply Voltage Range | -0.5 V to +7.0 V |
| I/O Drive Capability | Source 4 mA, sink 8 mA |
| I/O Compatibility | TTL compatible |
| In‑System Programming Voltage | 5 V only |
The device can operate up to 125 MHz.
It provides 96 universal I/O pins.
The supply voltage can range from –0.5 V to +7.0 V.
The typical propagation delay is 7.5 ns.