The SY10/100E107 offer five 2-input XOR/XNOR gates and are designed for use in new, high-performance ECL systems. The E107 also features a function output, F, which is the OR of all five XOR gate outputs, while F is the NOR. Both true and complementary outputs are provided.
The SY10E111AE/LE and SY100E111AE/LE are low‑skew 1‑to‑9 differential clock driver devices designed for high‑performance clock distribution. They operate from either 5 V or 3.3 V supplies, provide VEE output, an enable input, and feature voltage‑ and temperature‑compensated outputs.
The document lists electrical characteristics for PECL and ECL operation, ordering codes for commercial and industrial packages, and mechanical dimensions of the 28‑lead PLCC package. It also defines timing parameters such as propagation delay, skew, setup, hold, and release times.
| Power‑supply range (3.3 V version) | -3.0 V to -3.8 V |
|---|---|
| Part‑to‑part skew | 200 ps |
| Output‑to‑output skew | 50 ps |
The device fans out one input signal to nine identical differential outputs.
Both sides of each differential output must be terminated into 50 Ω, even if only one side is used.
The 3.3 V PECL version operates with VCC from +3.0 V to +3.8 V.
SY10E111AEJC and SY100E111AEJC are the commercial 5 V ordering codes (J28‑1 package).