The document describes the features and characteristics of the SY10/100E143 high-speed 9-bit hold register, designed for use in new, high-performance ECL systems. It features parallel input data interface, mode selection, clock inputs, master reset function, etc. The product is suitable for high-speed registers, pipeline registers, synchronous operation, and byte-wide parity applications.
The SY10E143 and SY100E143 are high‑speed 9‑bit hold registers designed for ECL systems. They support a minimum operating frequency of 700 MHz and can toggle up to 900 MHz, making them suitable for high‑speed and byte‑wide parity applications. The devices are available in a 28‑pin PLCC package and feature dual clock inputs, an asynchronous master reset, and selectable HOLD or LOAD modes.
The datasheet includes detailed pin assignments, electrical specifications such as VEE range (‑4.2 V to ‑5.5 V), propagation delays (600‑1000 ps), reset recovery time (700‑900 ps), and mechanical dimensions. Ordering codes for commercial versions are also listed.
| Minimum operating frequency | 700 MHz |
|---|---|
| Maximum toggle frequency | 900 MHz |
| VEE voltage range | -4.2 V to -5.5 V |
| Number of bits | 9 bits |
| Package type | 28‑pin PLCC |
| Reset recovery time (tRR) | 700‑900 ps |
| Minimum pulse width (tPw) | 400 ps |
| Rise/Fall time | 300‑800 ps |
The devices operate at a minimum frequency of 700 MHz.
Both devices have a 9‑bit wide register.
They are available in a 28‑pin PLCC package.
The VEE range is from –4.2 V to –5.5 V.