MICREL SY10E150 SY100E150 handbook

Update: 30 September, 2023

The SY10/100E150 is a 6-bit D latch with differential outputs designed for use in new, high-performance ECL systems. When both Latch Enables (LEN1, LEN2) are at a logic LOW, the latch is in the transparent mode and input data propagates through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the input data. The Master Reset (MR) overrides all other signals to set the Q outputs to a logic LOW.

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Publication date: 09 May, 2012

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PDF Link: MICREL SY10E150 SY100E150 handbook PDF