The SY10/100E150 is a 6-bit D latch with differential outputs designed for use in new, high-performance ECL systems. When both Latch Enables (LEN1, LEN2) are at a logic LOW, the latch is in the transparent mode and input data propagates through to the output. A logic HIGH on either LEN1 or LEN2 (or both) latches the input data. The Master Reset (MR) overrides all other signals to set the Q outputs to a logic LOW.
The SY10E150 and SY100E150 are 6‑bit D latches with differential outputs intended for high‑performance ECL systems. The device includes latch enable inputs, a master reset, and both true and inverting outputs.
The datasheet details the pin configuration, truth table, DC and AC electrical characteristics, package type, and ordering codes, along with mechanical dimensions for the 28‑pin PLCC package.
| Maximum propagation delay | 700 ps |
|---|---|
| VEE voltage range | -4.2 V to -5.5 V |
| Package type | 28‑pin PLCC |
| Typical power supply current | 52 mA |
| Typical reset recovery time | 750 ps |
The maximum propagation delay is 700 ps.
The VEE range is from –4.2 V to –5.5 V.
They are available in a 28‑pin PLCC package.
Typical power supply current is 52 mA.