This document describes a high-speed 9-bit shift register designed for use in new, high-performance ECL systems. It features both parallel and serial input capabilities and is suitable for applications such as diagnostic scan registers, parallel-to-serial conversions, and byte-wide parity.
The SY10E142 and SY100E142 are high‑speed 9‑bit shift registers designed for ECL systems, supporting serial or parallel data input and providing both serial and parallel outputs. The devices include selectable SHIFT or LOAD modes, dual clock inputs, and an asynchronous master reset.
Key specifications include a minimum shift frequency of 700 MHz, power‑supply currents of 120‑145 mA, propagation delays of 600‑1000 ps, and availability in a 28‑pin PLCC package. Ordering codes and package details are listed for commercial use.
| Maximum Shift Frequency | 700 MHz (min) – 900 MHz (typ) |
|---|---|
| Package Type | 28‑pin PLCC |
Applying a logic HIGH to MR asynchronously resets all nine registers to a logic LOW.
The device is available in a 28‑pin PLCC package.
They are fully compatible with industry standard 10KH, 100K ECL levels and Motorola MC10E/100E 142.