Update: 01 October, 2023
The SY10/100E111 is a low-skew 1-to-9 differential driver designed for clock distribution in new, high-performance ECL systems. They accept one differential or single-ended input, with VBB used for single-ended operation. The signal is fanned out to nine identical differential outputs. An enable input is also provided such that a logic HIGH disables the device by forcing all Q outputs LOW and all Q outputs HIGH. The device is specifically designed and produced for low skew. The interconnect scheme and metal layout are carefully optimized for minimal gate-to-gate skew within the device. Wafer characterization and process control ensure consistent distribution of propagation delay from lot to lot. Since the E111 shares a common set of “basic” processing with the other members of the ECLinPS family, wafer characterization at the point of device personalization allows for tighter control of parameters, including propagation delay. To ensure that the skew specification is met, it is necessary that both sides of the differential output are terminated into 50Ω, even if only one side is being used.
File format: PDF
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MD5 Checksum: C801629F939D500C0FD920F4B2F4562B
Publication date: 09 May, 2012
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PDF Link: Micrel ClockWorks SY10E111 SY100E111 Manual PDF